You need dual D/A's to generate such a display. The speed with which the outputs can be changed--which soon becomes the speed with which the outputs can be computed, is what limits the complexity of the display.
It would appear that a very simple circuit could be made for an experiment. The parallel printer card should be able to latch 8 bits
(unless it only uses 7, I don't remember). So a simple R-2R network or even 1-2-4-8 K resistors can make a dual 16 level DAC that will have an advantage of being set at once. Add 2 caps and a lot of software...A bit off-topic, but close enough. I have heard of an interesting technique of debugging uC systems in the early days when logic analyzers were not easily available. 2 R-2R DACs, 8 bits each on the low and high bytes of the 16 bit address bus connected to a X-Y scope allegedly gave a good idea of what the program was doing. Anybody ever heard this?
-Alex.