Alex Freed wrote:
Bryan Parkoff wrote:I have no idea how narrow or wide between clock bit on depending of rotation speed.For Example: "_" is zero bit. "1" is 1 bit. ___1____1________1____1____ 280 RPM _____1______1__________1______1______ 300 RPM _______1________1____________1________1________ 320 RPMA little elementary school level math and a calculator can help :) If the nominal delay between consecutive 1 bits is 4 uS at 300 RPM, it will be 4 * 300 / 280 =~ 4.29 uS and 4 * 300 / 320 = 3.75 uS at 320 RPMSo after you detect a 1 bit, see if there is another pulse in the interval from 3.75 to 4.3 uS. So sampling at 2 MHz will not get youa full resolution. 4 MHz is much better: you can sample at 3.75, 4.0 and 4.25 uS.
Of course, sampling at 2MHz works fine, and tolerates an even greater range of speed deviations within a nibble, as Sather describes very nicely. This is important, because speed variations affect both the writing and the reading drive, which can double the effect if they are in opposite directions. (In the case of a disk written and read by the same drive, only short-term speed variations are an issue.) There is no prize for enforcing tight limits on disk speed. ;-) The real issue is the tolerance for *two* consecutive zeroes, since the off-speed timing error is cumulative. In practice, the limit on consecutive zeroes is set both by read amplifier AGC and by speed tolerance. -michael NadaPong: Network game demo for Apple II computers! Home page: http://members.aol.com/MJMahon/ "The wastebasket is our most important design tool--and it's seriously underused."