Re: Transwarp II photos posted online

["Randall Flagg" <rfs_no_spamz_@apple2.com>]

Your specs seem to match this advertisement: 
http://www.satanz-host.de/pic/apple/DC65.png

... but it is a bit more expensive :-)))

"Ralf Kiefer" <R.Kiefer.SPAM@gmx.de> schrieb im Newsbeitrag 
1i3gxkr.g2cliz1t4dckmN%R.Kiefer.SPAM@gmx.de">news:1i3gxkr.g2cliz1t4dckmN%R.Kiefer.SPAM@gmx.de...
> Marcus wrote:
>
>> http://en.wikipedia.org/wiki/Apple_II_accellerators
>
> Oh, they've forgotten some more accelerator boards used in the Apple ][
> and Apple //e.
>
> After having used my AEs Transwarp @3,6MHz for some years I upgrated my
> Apple //e a little bit:
> In 1988 (or 1987?) I bought an accelerator board constructed by a
> two-man-company in the south of West Germany (Leinfelden-Echterdingen).
> I actually do not remember the company's name :-(  They did this mainly
> to accelerate a chess computer. At this time these were mostly based on
> the 6502. But they used the Apple ][ bus and offered this card also to
> Apple users mainly running the processor with the NMOS instruction set
> @10MHz. There were some cards running @12.5MHz and mine was running the
> CMOS instruction set in a //e.
>
> This card was build on two full length boards. Power consumption is 5A
> @5VDC. I had to upgrade the power supply and added a fan (real Pentium
> feeling ;-) ).
>
> The processor was based completely on PALs and standard TTLs.
>
> The whole main memory of an //e was held onto this card (144kB SRAM
> @50nsec, in 1988!). There is no code caching. The processor is forced to
> synchronous 1MHz by hardware only running the low level disk driver at
> slot 6. Screen memory is mirrored and written to mainboard memory in
> background but never read from slow mainboard memory. The whole set of
> soft switches is implemented "onboard" for reducing unnecessary access
> to mainboard RAM. I/O except slot 6 is implemented "a bit" asynchronous.
> If the last write access in background has not finished yet the fast
> processor idles (in hardware) while waiting. Read access to slot
> addresses is handled synchronous too.