Re: BYTE Article of Mega II

["Michael J. Mahon" <mjmahon@aol.com>]

David Wilson wrote:
> On May 16, 6:18 am, "Michael J. Mahon" <mjma...@aol.com> wrote:
>
> > A 3000-gate "gate count" is not particularly complex, even by the scale
> > of 1984.
> >
> > "Gate count" usually refers to the number of 2-input NAND gates, and is
> > often conventionally treated as one-third the number of transistors.
>
>
> I found an IEEE paper that gives 3 NMOS transistors or 4 CMOS
> transistors per gate.
> http://ieeexplore.ieee.org/iel1/41/723/00019060.pdf?arnumber=19060
>
> I also have a vague memory that the 6800 was so named because that was
> about how many gates it contained. The IEEE paper lists it as ~4000
> transistors.

ISTR a similar number, closer to 3000, for the 6502...

Transistor counts are always a bit problematic, since many resistors are
actually implemented as transistors.  And the fact that MOS processes
allow "transfer" gates (bidirectional switches) makes comparable gate
counts dicey as well.

Virtually all LSI "counts" are just estimates, made by summing the
approximate numbers for many functional blocks.

About half of the 6502 is very regular, with 30% ALU and about 20%
decode ROM.

> > Since 64Kbit DRAMs were pretty commonplace in 1984, with transistor
> > counts of 65000+, a gate count of 3000 seems like a pretty simple ASIC.
>
>
> I think regular arrays like memory chips would pack more tightly than
> random logic.

Quite true, but an order of magnitude should more than compensate for
the less regular interconnect of logic.  ;-)

-michael

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