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Re: Focus HD -> CF Questions

mdj wrote:

On Mar 7, 6:35 am, "Michael J. Mahon" <mjma...@aol.com> wrote:


aiiad...@gmail.com wrote:



I think all you can do is get better media device with a faster seek
time...


It can't be seek time--a CF card doesn't have any to speak of.

It's the byte-by-byte programmed data movement on a 1MHz machine that
is the limiter, and I doubt that there are any plans for a DMA version
that could, in principle, sustain a 1MB/sec maximum bandwidth.



On the IIe you're also limited by the single block 'funnel' IO model
of ProDOS which probably impacts throughput just as much, since
there's never any multiblock transfers.


Good point--there are limitations both on the peak transfer rate
and on the average transfer rate.


In fact, those of us with accelerated //e's would have to turn off the
DMA it it had it.  ;-(



It's debatable that there's any practical difference between DMA on a
non-accelerated IIe vs. non-DMA on an accelerated IIe. At least on my
setup (Transwarp I, Apple SCSI) using the accelerator in conjunction
with a Rev C SCSI card is actually as fast or faster than a high-speed
SCSI without the accelerator.


My experience is similar.


It'd be nice to have the best of both worlds, but I'm unconvinced that
accelerated PIO would end up being percievably better than accelerated
DMA anyway, and unfortunately there's no way to test it, unless
somebody has one of the fabled Transwarp III's lying around.


The maximum DMA rate is 1MB/sec, set by the peripheral bus.

The maximum programmed I/O rate, even with infinite acceleration, is
also limited by the number of peripheral bus reads and memory writes,
since they can only run at 1MB/sec, combined.

If the programmed I/O is written in such a way that the code resides
in cache, and only registers are updated in the inner loop, then there
is one PIO load and one data store to memory, and the loop could move
data at 0.5MB/sec.  However, if the inner loop is written in such a way
that memory is modified for other than data transfer, that modification
bandwidth comes out of the maximum 1MB/sec bus budget.

Of course, for a 6502, it will be necessary to update a pointer
periodically, in the outer loop, but that effect is second order.


On the IIgs the game is different, since GS/OS is considerably
smarter.


Though both DMA and the PIO read are still limited to 1MB/sec,
the memory can be accessed faster.

-michael

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Home page:  http://members.aol.com/MJMahon/

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