Re: 6502 trashing memory cycles...

["bieling@terra.es" <bieling@terra.es>]

On 7 mar, 03:26, "mdj" <mdj....@gmail.com> wrote:
>
> Your accelerator could end up being more complex than the Apple II :-)

I think that a circuit to flag these cycles may be quite simple:

-A combinatory logic block in which the input is the opcode and the
output are six bits, the state of these output bits (one for each of
the six forthcoming memory cycles) flags the cycle as "borrowable" or
not. These 6 bits fed the input of:
-A parallel in serial out shift register that is loaded during SYNC
marked cycles (during opcode fetchs), and clocked by phase 0.

Unless I'm missing something, more or less, that's it.

> In any reasonable accelerator design, when running high speed it hits
> high-speed memory, so there's no problem, and it that mode you can
> break any cycle timing rule you like.
>
> Of course, insisting on using a 'real' 65c02 in such a design imposes
> a number of constraints on the optimisation you speak of, so you'd be
> better with programmable logic, where you can optimise it to the point
> where the worst case cycle time is 3.

Yes, but honestly, I don't feel like I could design a 6502 compatible
processor. And, if such a thing were done, it ought to have a 100%
6502 compatible mode, and this would complicate the design even more.

> Although why you'd do this, and
> not just up the clock speed of the accelerator until you reached the
> glass ceiling speed I am not sure.
>
> Matt

I'm trying to draw a thick line between the "processor module" of the
accelerator and the "interface to the Apple II" module, so that the
processor can be replaced by a faster one in the future.

The nice thing about just-thinking-about is that you don't need to
pick up the solder... :-)
Of course, once the design is finished ,there's nothing like doing it
and seeing it work (*) !

Jorge.

(*)never at the first time.