Re: 6502 trashing memory cycles...

["bieling@terra.es" <bieling@terra.es>]

On 5 mar, 12:54, Mark McDougall <msmcd...@no.spam.iinet> wrote:
> biel...@terra.es wrote:
> > I'm not saying that the 6502 doesn't internally do something useful
> > during that cycles.
> > I'm saying however that whatever it is, during these cycles, accessing
> > the memory is not neccesary.
> > During these cycles it does un-needed memory accesses.
>
> But my point is that it *is* necessary in _some_ of these cases, even if the
> result is not used, for the reasons I gave earlier.
>
> Regards,

Yes, one example of what you say is a BEQ/BNE. Both waste a cycle
reading then next address after the opcode, even though the branch may
not be taken (and the offset read at the next address not needed). I
imagine that during this extra cycle the decision is taken inside the
6502. And there's no easy way to know from the outside if that 2nd
cycle can be stealed or not, unless you knew the state of the Z
flag...

But, If the 6502 was running at some extravagant 14 Mhz for example
(*), the probability of being able to steal 40 cycles in a 40
microseconds (***) time lapse would be an infinitesimal away from 1, I
think. Enough (**) to re-create a line of video without wasting any
memory bandwith... !

(*) Figure 6.2 in page 24 of the WDC's 65c02 datasheet.pdf, shows in a
graph fMax as being 20Mhz. The table 6.3 on page 25, OTOH, doen't show
a.c. values for anything higher than 14MHz. What's fMax then, 14MHz or
20 MHz ?
(**) There are 14*40=560 ! phase 0 cycles in 40 microseconds if
running @14MHz. 40 out of 560 is a mere 7.1%.
(***) And in fact, the time lapse between succesive video scan lines
is more than 40 microseconds.

Jorge.