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Re: 6502 trashing memory cycles...
bieling@terra.es wrote:
> On Mar 4, 9:11 pm, "Bryan Parkoff" <nos...@nospam.com> wrote:
>> Why do you think this way? Let me give you the information below. I
>> don't think 3 out of the 6 cycles of an RTS are useless.
>>
>> Cycle Address Bus Data Bus External Operation Internal Operation
>> 1 0300 Opcode Fetch Opcode Finish
>> Previous Operation, 0301 + PC
>>
>> 2 0301 Discarded Data Fetch Discarded Data Decode RTS
>>
>> 3 01FD Discarded Data Fetch Discarded Data Increment
>> Stack Pointer to 01FE
>>
>> 4 01FE 02 Fetch PCL Increment
>> Stack Pointer to 01FF
>>
>> 5 01FF 01 Fetch PCH
>>
>> 6 0102 Discarded Data Put out PC Increment
>> PC by 1 to 0103
>>
>> 7 0103 Next Opcode Fetch Next Opcode
>>
>
> Yes, memory cycles 2,3 and 6 are useless, wasted.
> An external circuit that knew that could put them to better use : to
> generate sound, or to read from the video frame buffer, or for DMA,
> or... ?
>
> Jorge.
The extra reads may not serve an amazing amount of use but catching them
would be nontrivial. I may be wrong but it would be easier to reimplement a
6502 on an FPGA with the extra circuitry built in to tristate the outputs
during certain cycles.
That kind of design would interfere with sound generation with the
softswitch and may cause RAM refresh problems.
I'm now thinking of the C=64. The clock model on that is enough to give me
nightmares. It wastes very little and uses both phases of the clock too.
Even the VIC-II counts cycles to know the soonest time it can start
stealing cycles.
I don't remember. Does the apple][ use one half of the clock or both?
Tristan.
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