Re: IIgs video modes...

["Charlie" <charlieDOTd@verEYEzon.net>]

"jsnospam@cimmeri.com" <js@cimmeri.com> wrote in message 
1172592265.115580.268460@q2g2000cwa.googlegroups.com">news:1172592265.115580.268460@q2g2000cwa.googlegroups.com...
> On Feb 27, 7:31 am, demp...@actrix.gen.nz (David Empson) wrote:
>> The horizontal line is the same width in SHR and other video modes,
>> implying the same time (about 40 microseconds) for the active portion of
>> the row, so it must have a higher frequency dot clock in order to fit
>> 320 or 640 pixels in the same space as 280 or 560 for other modes.
>
> David, have you actually verified that they are the same width with
> your eyeballs and a ruler?  Just curious if this is an established
> fact now.

I can verify what David said.  I measured the borders with a ruler.  The 
left border width is identical in 80 column text mode as in 640 SHR.  The 
right border is very slightly smaller for the 640 SHR (about 1/16 inch on a 
16-1/8 inch wide screen) which I believe is essentially the same.  The 
bottom border, of course, is smaller with SHR.

>
>> If I remember right, the IIgs has a master clock frequency of 28.63636
>> MHz. Deriving 8.18181 from that is reasonably OK: a divisor of 3.5, i.e.
>> 7 half cycles. It would be harder to derive 16.36363 MHz, which would
>> require a divisor of 1.75. DPLL, perhaps?
>
> Looking at the IIgs schematic, the VGC has both a 14M and 28M clock
> input.   28M is generated by a dedicated oscillator nearby.   The only
> other signals of interest are coming from a chip named SERCLK which
> itself is driven by a 32.768khz crystal, and is powered at times by
> the Lithium Battery.  I suppose this is a clock chip.
>
> This clock chip is for some reason connected to several of the VGC
> inputs -- CLKCS, DATA, CLK, 1SEC, and 3.5DIK.   Not sure what that's
> mean, but David mentioned 3.5 divisor above.  A bell has rung.
>

The hardware manual says the VGC internally generates a 1 second interrupt 
and the scan line interrupts.  I guess it uses the Real Time Clock to know 
when to generate the 1sec interrupt.  The 3.5DIK line doesn't come from the 
clock chip (at least not the schematic I have) but goes from the VGC to the 
disk drive connector as the 3.5"/5.25" drive select.  That I really don't 
understand!

Charlie