Re: Apple //e's RGB Card To Apple IIgs' RGB Monitor

["Alex Freed" <alexf@mirrow.com>]

"mdj" <mdj.mdj@gmail.com> wrote in message
1166698031.100088.301550@a3g2000cwd.googlegroups.com">news:1166698031.100088.301550@a3g2000cwd.googlegroups.com...
>Would one of the
> experts here care to explain the development toolchain, and if possible
> elaborate on a design for this using a GAL? I assume it's a matter of
> coding up a ROM with 4 bit addressing and 12bit words and hoping it
> fits.

OK, let's talk about modern CPLDs. They are as cheap as the much simplier
GALs and easier to program.

For example Xilinx's XC9536. The software to compile Verilog (or VHDL) code
is
free from Xilinx's web site. There are very similar devices and tools from
Altera,
Atmel and others.

You describe the functionality in Verilog. For example the 4 input bit table
lookup
can be coded as a trivial CASE statement - similar to "switch"  in "C".

Something like this
---------------
module lookup (input_addr, clock, result);
input [3:0] input_addr;
input clock;
output reg [10:0] result;

 always @(posedge clock) begin
  case (input_addr[3:0])
  4'b0000:
    result <= 11'b00000000000;

  4'b0001:
    result <= 11'b00000000111; // whatever the value should be
    .......................
  etc.
  endcase
 end
endmodule
----------------------

This assumes you have a clock and all the transitions should happen on this
clock.


Then you start the synthesizer and end up with a bunch  of reports and a
binary file used to
"burn" the CPLD. Can be done via a parallel port with just a few resistors.

This design will only use a tiny part of the $1.50 CPLD. You can add for
example a shift
register to convert serial to parallel for free.

Hope this answers the question.

-Alex.