Re: Request a discrete refresh circuit schematic

["PZ" <skierpaul@yahoo.com>]

Bryan:  I think Ed wants to put an inverted 68pin PLCC socket on top of
the FPI/CYA chip and tap the ABUS and DBUS directly that way; thus his
need to generate his own refresh signals.  Neither IC is socketed on
ROM 01s or 03's, so it could be an easy universal implementation if the
board can be made small enough.

Ed:  I'd take a look at an old Apple II+ Schematic.  I've never peeked
at the refresh circuitry there directly, but that would probably give
you the best implementation using Apple II timing signals.  It should
be all there, you just need to scale things a bit.

- Paul

Bryan Parkoff wrote:
> "Bill Garber" <willy46pa@comcast.net> wrote in message
> J6GdnYNI18fr05HYnZ2dnUVZ_vqdnZ2d@comcast.com">news:J6GdnYNI18fr05HYnZ2dnUVZ_vqdnZ2d@comcast.com...
> >
> > "Ed Eastman" <noone@nowhere.net> wrote in message
> > news:eeh3qo$2s6$1@unlnews.unl.edu...
> > : Since there is no A2 hardware forum, I'll post it here...  (Sorry about
> > : posting to the emulators group.)
> > :
> > : I need a circuit to refresh some stand alone ram for a RAM expansion
> > : circuit I am designing.  (12M Ram on the IIgs)  I understand the basic
> > : theory but I need an actual circuit with real RAM chips to help me
> > : visualize the process. I've looked on the internet but the refresh
> > : circuit is always glossed over and people are using a memory manger or
> > : some such chip that I don't have access to.
> > :
> > : Would someone please send me a discrete schematic of a refresh circuit
> > : on say, a 4 meg bank of RAM?  Or I'd be just as happy with a point to
> > : some resources readily available via internet or book reference.
> > :
> > : I forgot to mention I'd like to use some old 8bit SIMMs I have laying
> > : around.  Of course the circuit would be just as easy on a 72 pin simm.
> > :
> > : Thanxk,
> > : Ed
> > : eeastmanNO@SPAMgmail.com
> >
> > Ed,
> >
> > I sent you a private message. I hope you
> > get it, because there is a lot of info in
> > there. Let me know.
> >
> > Bill Garber
> > Owner - Garberstreet Enterprizez
> > Co-owner - GSE-Reactive.com
> > (610)935-7676 (610)329-8996
> Hello,
>
>     The problem is that Apple IIgs' motherboard is limited to 8 MB of RAM.
> I doubt when you try to expand RAM to 12 MB.  It may be accessible maximum 8
> MB leaving free 4 MB RAM.  Do you think what you need to modify the logic on
> motherboard to break the limit of 8 MB?
>     Think of Apple IIgs ROM 03.  It has 1.25MB built in.  You add 8 MB of
> RAM to be 9.25MB, but it is still accessible to 8 MB.  I wonder.
>     Between $80 and $DF banks are for ROM like firmware of TransWarp GS on
> $BC bank and RAM Keeper.
> 
> Bryan Parkoff