PZ wrote: > It might have worked fine had you used (8) 1M x > 4's, however 4v logic levels (due to lack of drive to the pins of all > 32 DRAM chips) don't equate to a reliable implementation. I'm not familiar with the ins and outs of the IIGS's address decode arrangement on the expansion connector, but in case, only 8 DRAMS are going to be driven for any given memory read/write. Matt