Re: Read full 8-bit character from serial port?

[dempson@actrix.gen.nz (David Empson)]

<bieling@terra.es> wrote:

> >I can't find anything clearly stating its behaviour either way. I
> >suggest you have a look and try to find something to justify your
> >theory.
> 
> < http://www-clips.imag.fr/projet-systeme/Z85230/chapter7.pdf>
> Page 7.3
> 
> "The receive buffer must be read before the recently re-
> ceived data character on the serial input is shifted into
> the receive data FIFO. This FIFO is three bytes deep.
> Thus, if the buffer is not read, the fifth character just ar-
> rived causes an overrun condition. There is no bit that
> can be set or reset to disable the buffering."

This directly contradicts a separate section in the SCC manual which is
talking about the ESCC (Z85230), which has an 8 byte FIFO.

Section 2.4 of the same manual, page 2-22

<http://www-clips.imag.fr/projet-systeme/Z85230/chapter2.pdf>

"WR7' D3=0, a receive interrupt is generated when one
byte is available in the FIFO. This mode is selected after
reset and maintains compatibility with the SCC. Systems
with a long interrupt response time can use this mode to
generate an interrupt when one byte is received, but still allow
up to seven more bytes to be received without an overrun
error. By polling the Receive Character Available bit,
RR0 D0, and reading all available data to empty the FIFO
before exiting the interrupt service routine, the frequency
of interrupts can be minimized."

If this section was talking about the original SCC it would say "... but
still allow up to two more bytes to be received without an overrun
error."

In this case, the complete reception of the fourth byte would cause an
overrun.

Looks like I'll have to do a real test with the IIgs (or an ESCC, which
I have access to at work) to prove it one way or the other.

-- 
David Empson
dempson@actrix.gen.nz