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Re: IIgs RGB to VGA experiment

mdj wrote:

Michael J. Mahon wrote:



No, you'd need a voltage regulator--but that's not a problem.

As mentioned above, changing the operating voltage of the whole
board is not the best way to adjust sampling frequency.  ;-)



I'm surprised there's not a trimpot on the board of the device to
adjust its sampling frequency.

Could this be a result of the IIGS not outputting it's signal at
exactly 60Hz ? I'd expect that whatever technique the device uses for
conversion, it would need to synchronise the vertical refresh of the
output to the input to avoid rolling, tearing, or other effects. If the
IIGS is a little off, the device would have to compensate its
horizontal scan rate accordingly. Connecting to a TV may not be a good
way to determine the IIGS behaving exactly according to its
specifications.

I'm assuming that such a device either buffers one or two scanlines
(harder) or an entire display sweep (easier) in memory, then reoutputs
it at as close to VGA'ish frequency it can manage, while remaining
synchronised with it's input.

Of course, this is guesswork based on how I'd build such a device
myself - the actual device might operate completely differently, though
somehow I doubt it. 

The most common, and IMHO best, approach is to buffer two lines and
generate an output signal with exactly twice the horizontal scan rate
as the input (and the same vertical rate, of course).

The tricky part is the sampling clock.

Ideally, you would like to phase-lock the sampling clock to the
residue of the dot clock on the incoming video signal--14MHz (or
some multiple) in the case of the Apple II.

If the sampling clock is not phase-locked to the Apple dot clock,
there will be visually annoying artifacts as the Apple "pixels"
migrate back and forth across the sampling clock "mesh".

If phase lock is not attempted, an acceptable result could be
achieved (at the cost of faster circuitry and more memory) by
oversampling by at least 3x, for a sample clock of over 40MHz.

For a converter designed with, say, a PC CGA signal in mind, it
would be reasonable to phase-lock to the horizontal sync and
use a sampling clock that was a multiple of horizontal sync
frequency appropriate to the expected resolution (dot clock)
of a PC CGA display.  That frequency is different from the
Apple dot clock, and would result in "horizontal jitter" of
pixels, that is very annoying in, for example, a text display.

-michael

Parallel computing for 8-bit Apple II's!
Home page:  http://members.aol.com/MJMahon/

"The wastebasket is our most important design
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