Re: 6502 illegal opcodes questions

[Eric Smith <eric@brouhaha.com>]

Michael J. Mahon
> True, but the decoding in the 6502 is handled by a kind of PLA, so
> it would likely not be very expensive (in real estate) to trap or
> NOP the invalid combinations.

Bruce Tomlin wrote:
> Nope, it's handled by good old random logic.  A PLA is designed to be a 
> programmable generic replacement for random logic, and is way too 
> inefficient for high-volume VLSI.

Sorry, but Michael is correct.  It is definitely a PLA.  You can see it
on the die (or a photomicrograph); it's the most regular structure.  It
is near one edge of the die, takes up an area about 1/6 of the long
dimension of the chip by most of the short dimension.

If I've counted correctly, the logical size of the product term array is
21 inputs by 137 product terms.  15 of the inputs are from the
instruction register; they are the true and complement forms of each bit
except bit 1.  It appears that two inputs come from the clock generator,
and four from a state counter, but I haven't studied it in enough detail
to be certain of that.  Most of the product terms control gating of
signals between registers.

MOS PLA design is actually quite space-efficient, and for functions like
instruction decode is usually more space-efficicent than equivalent
random logic would be.  This is especially true of the NMOS 6502, for
which the instruction encoding was designed in such a way that they did
not need to OR together many (any?) of the product terms.

It's not a *field* programmable logic array, if that's what you were
thinking of.  It's mask programmed by the presence or absence of
transistors at specific locations in the array.

Many microprocessors in the 1970s, and almost all newer ones use PLAs
for instruction decode and other tasks.  Even the lowly TMS1000 four-bit
microprocessor, the epitome of cheap microprocessors in the mid-1970s,
used PLAs.

Eric