Re: RFC : SOME IDEAS FOR THE APPLE II FPGA'ers

[Mark McDougall <markm@vl.com.au>]

Jorge Chamorro Bieling wrote:

> Dou you think that this can ever run as fast as a hardware
> "emulation" ?

Regardless of the underlying architecture, whether RISC or not, *any* 
process that requires translation is always going to be slower than a 
fully optimised, native implementation. Period.

If you're really interested in pushing the limits in terms of speed, you 
have 2 options:

1. Implement a native 6502 to run as fast as possible. Of course the 
core only has to be instruction set compatible, you can redesign the bus 
architecture whatever way you like.

2. Write an emulator for whatever processor you can clock at ridiculous 
speeds (much higher than you can clock an FPGA) and hope that you can 
optimise it enough to outpace option #1. Don't forget you need to 
emulate all I/O in the system including video, which takes a large chunk 
out of your headroom.

To suggest you can emulate a 6502 on a RISC processor core within an 
FPGA faster than a native optimised 6502 implementation is utterly 
ludicrous.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266