Zip Chip programming info / disk image?

["RedskullDC" <RDC@oz.org>]

Hi All,

Can anyone point me towards more info on how the
Zip chip (2+, 2e versions) are programmed, and/or
a dsk image to drive the things?

I've gleaned a certain amount from previous posts:

53ms timer on the /DEVSEL signal.
Turning certain slots on/off for speed slowdown.


Reason I ask:

I'm tooling around with recreating the thing in an
FPGA.
I've already got a Spartan IIe board to emulate a
1MHz 65C02 ok (still testing...) with a jumper lead to
the 65C02 socket in my 2e.
I can post pics if people are interested, and source code
when I'm satisfied everything is working alright.
(Using one of these: http://www.burched.biz/b5x300.html
that I already had here from another project.)

I have a Spartan3-400 starter board from XILINX on
the way, which is probably easier for most people to get,
so it can easily be ported across to that.
They're pretty good value for $120US. ($99 for the -200
version S3)

Next I'd like to get the board working as a zip-chip.
Once that is working, the next thing will be to move
the video generation into the FPGA, so as to be able to
output standard VGA frequencies, and also to allow
the "zip-chip" to run at full speed when accessing video.
More colours/screen modes are a possibility.

The 2e could easily be replicated in the FPGA entirely,
but that would render all your peripheral cards useless,
plus it would mean a lot more work re-inventing the
wheel in many cases, which is why I have chosen to do
things this way.

Cheers,
Red