bieling@terra.es wrote:
Yes you're right. But as you can't modify the Apple II timing this complicates the access to the RAM from the side of the video generator. If it were not because dual-ported RAM seems to be so much more expensive. Still, it may fit in the fpga in the form of ip. I believe it would ease the things a lot.
If an FPGA is used, the internal BRAM (block RAM) is organized as dual port memory anyway, so it's a no-brainer. If the card is built with regular RAM (say the surplus cache chip from an old 486 motherboard) and discrete logic and/or CPLDs then transparent video RAM access is still quite simple. Run the board clock at say 8 times the Apple clock and read the video RAM 4 times during the 500 nS of the Apple 2 video cycle. As you said the dual-ported RAM is quite expensive. Old cache RAM is virtually free.