zwsdotcom@gmail.com wrote:
Actually the ARM is the RISC micro you're most likely to need to hand-optimize. Writing high-performance ARM code, especially when interrupt latency is a problem, involves dancing between 32-bit and Thumb modes, and _very_ careful juggling with register usage.
Most processors are going to benefit from a bit of hand-coded assembly in an ISR, so your point is moot.
What Peter was getting at is that writing hand-optimised assembler is an art form at the best of times, and doubly so an a RISC architecture. Someone cutting their teeth on assembler is much better off on a CISC than worrying about the branch pipelines and shuffling data between 128 registers...
Regards, -- | Mark McDougall | "Electrical Engineers do it | <http://members.iinet.net.au/~msmcdoug> | with less resistance!"