Re: Cycle by Cycle Problem?

["josephoswaldgg@hotmail.com" <josephoswald@gmail.com>]

sicklittlemonkey wrote:
> > The only detectable effects on the ordinary hardware are the
> > synchronization of the video memory accesses
>
> The video scanner's low bit, H0, is synced with the long cycle.
>
> > simulating this level of detail would be necessary for simulating
> >"Vaporlock" and mixed-video softswitching
>
> I can assure you that it is not. ;-)

I guess the "this level" is somewhat ambiguous. I was referring to
synchronizing the memory accesses at the 2 MHz rate, not the 14 MHz
clock that Bryan was referring to.

In any case, it seems obvious to me that, one way or another, the data
transfers from RAM to the video registers have to be synchronized with
the transfers from unmapped I/O locations (i.e. floating bus) to CPU
transfers for Vaporlock to work. Maybe you can special case this,
trapping only floating-bus-location references, but you've got to have
exact information about how many CPU cycles have happened since the top
of the video field to figure out what vapor to present, don't you?