Re: How many times must Apple make such DRASTIC architecture changes?

[abuse@vindaloo.cabal.org.uk (Peter Corlett)]

Michael J. Mahon <mjmahon@aol.com> wrote:
[...]
> Hopefully, we'll see an end to 30+ stage pipelines that blow away
> huge numbers of in-process instructions on every "surprising"
> branch, and fewer four-level deep caching systems that only work
> well for little loops with little data sets--but get the GHz rating
> up. ;-)

One notable "surprising branch" is interrupts. I'm told that interrupt
latencies have barely improved since the 6502, which took about a
microsecond.

-- 
Do not worry about your problems with mathematics, I assure you mine are far
greater.
							- Albert Einstein