Re: 6502 CPU's Read/Write Question

["josephoswaldgg@hotmail.com" <josephoswald@gmail.com>]

Bryan--

  On further inspection, your repeating of "Cycle 4" indicates we may
be misunderstanding your question. It seems you might be considering
multiple points during Cycle 4, but not during the other cycles.

  For simplicity, most people will only consider a single point in the
cycle, which represents the final outcome of the operation. In that
view, there is only one operation in Cycle 4, which is to Write the
data $41 to address 2001.

  It may be that depending on the exact delays for various control
lines that the data bus may have momentarily "wrong" data. The point
is, however, that the system is designed so that there is sufficient
margin that the right data is used for the right operation: that is,
the RAM is designed to read data from the bus when the Write signal is
asserted, and will stop driving the bus some short time after the R/W
line goes low at the chip input, and the CPU and other circuitry is
designed so that the data is forced on the bus early enough before the
R/W signal is asserted that the correct data is always present when the
chip needs it.