Re: 6502 CPU's Read/Write Question

["Bryan Parkoff" <nospam@nospam.com>]

Michael,

    I understand that R/W is always the read default.  Please verify to make 
sure that my steps are correct during cycle 4.

Bryan Parkoff

"Michael J. Mahon" <mjmahon@aol.com> wrote in message 
iMGdnW6LqLqATdnfRVn-hA@comcast.com">news:iMGdnW6LqLqATdnfRVn-hA@comcast.com...
> Bryan Parkoff wrote:
>>     6502 CPU has R/W pin.  Is it possible that all instructions are 
>> always
>> set to read only unless R/W pin is turned on to tell some instructions to
>> set to write only.  It uses STA instruction for read first then write.
>>
>> For example:
>> Cycle 1: Address Bus: 1000  Data Bus: 8D -- Read only
>> Cycle 2: Address Bus: 1001  Data Bus: 01 -- Read only
>> Cycle 3: Address Bus: 1002  Data Bus: 20 -- Read only
>> Cycle 4: Address Bus: 2001  Data Bus: C1 -- Read only (Old Data)
>> Cycle 4: Turn on R/W pin  -- Read $41 from Accumulator
>> Cycle 4: Address Bus: 2001  Data Bus: 41 (New Data)
>>
>>     It is like ASL using RMW.  What do you think?
>
> The "default" state during a bus cycle is READ.
>
> /WRITE is only asserted when there is something to be
> written.  ;-)
>
> -michael
>
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