Moll wrote:
Michael J. Mahon wrote:It would be quite difficult to write RWTS in a real-time OS environment. Even when interrupt latency is just a few microseconds, by the time you've executed a few dozen instructions, you could be off my many microseconds, depending on cache hits and misses. Of course, one could just stop depending on cycle-accurate instruction timings--but that wouldn't be an Apple II.What about cycle accuracy in 8-bit mode only?
That could be done, and was what I was referring to as "lockstep" mode, where the CPU's internal operations would be synchronized to the bus. However, this would amount to a _huge_ slowdown, and few designers would consider this mode interesting enough to put up with its inevitable encumbrances on an otherwise fast design. -michael New Applesoft BASIC interface for NadaNet networking! Home page: http://members.aol.com/MJMahon/