Re: Replacing the 6502 with a faster chip

[salfter@salfter.diespammersdie.dyndns.org (Scott Alfter)]

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In article <20040820130353.10918.00002564@mb-m25.aol.com>,
Michael J. Mahon <mjmahon@aol.com> wrote:
>Rob Jones replied:
>>Is the 65C02 a pin-for-pin compatible with the 6502? I could very
>>easily make a 3X PLL (3MHz) to clock the "C" while keeping the bus at
>>1X (1MHz).
>
>Simply clocking it faster will not allow it to interface with the
>1MHz bus and memory interface.  You need to make the rest
>of the Apple II _completely unaware_ that the processor is
>running faster, which means that the fast processor must have
>its own faster memory, either as an associatively mapped cache
>or as a complete copy of the content of standard Apple RAM
>(including any expansion memory if you want to run faster on
>those accesses).

You also need to provide some means for the accelerator to disable itself
for certain timing-critical activities, such as accessing floppy disks. 
That adds an additional layer of complexity, as you'd most likely implement
this functionality by monitoring the address bus for accesses to certain
address ranges and slowing down/speeding up appropriately.

  _/_
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