Re: Replacing the 6502 with a faster chip

[David Wilson <david@uow.edu.au>]

robsgreenneon@startmail.ca (Rob Jones) writes:
>Is the 65C02 a pin-for-pin compatible with the 6502? I could very
>easily make a 3X PLL (3MHz) to clock the "C" while keeping the bus at
>1X (1MHz).

Yes (although some versions have /ML available on pin 5 I believe).
ML is a memory lock signal used in multiprocessor systems to ensure
that read-modify-write instructions are atomic.

How can you clock the 65C02 at 3MHz while running the bus at 1MHz?
Every machine cycle on the 6502/65C02 is a bus cycle as well. There
are no "unused" bus cycles [that can be identified].

The 65816 has VDA & VPA pins which can be used to detect internal
bus cycles that do not need an external bus cycle - these could
be sped up were it not for the fact that devices like the Disk II or IWM
rely on these cycles taking place. Read the Caveats section of the 65816
data sheet...
-- 
David Wilson  School of IT & CS, Uni of Wollongong, Australia