Re: GCR Encoding

[mjmahon@aol.com (Michael J. Mahon)]

sean weintz wrote:

<snip>

>Apparrently you do not understand sync headers at all. Sync headers use 10
>bit bytes, right? (all apple GCR sync bytes are 10 bit normally) so nibble
>anylyzers
>cannot read them accurately. for instance they would read (or actually the
>controller
>would read):
>
>01111111101111111101111111
>and
>001111111100111111110011111111
>
>as being exactly the same thing, (namely FF FF FF) which of course they
>ain't.
>In fact, that use to be a halfway decent way to throw off nibble copiers -
>drop one sector off the track, and fill the space with 9 bit self sync bytes
>instead of 10 bit. Nibble copier will think they are 10 bit self sync bits
>and overwrite the track start on the copy! (that is before the algorithms in
>nibble copiers got smarter)

This is not so.  A clever disk read algorithm can determine not only
_that_ the high bit of the disk controller shift register went high, but
_when_ it went high, enabling the software to deduce how many
0's were written in between.

This 'bit stuffing" of disk nibbles was, in fact, one of the cleverer
copy protection schemes, since, at first, no copier preserved the
extra 0's and the time they took up.

How the Disk ][ is _designed_ to work is really quite interesting
and a marvelous engineering feat, but how it can be used outside
its intent is also marvellous ("spiral" tracking comes to mind ;-).

For all its sophistication, Woz designed the controller read state
machine to use a simpler "open-loop" bit timing method, since it
was adequate to his needs.  It is also possible to design an
adaptive bit timing approach, which would be very tolerant of
speed variations, and could bypass the ambiguities of more than
two consecutive 0 bits.  How many additional codes could be
used with such a scheme is an open quesition, but it might
come a lot closer to 128.  ;-)

In fact, if _any_ transition could be used to "center-up" the
bit window, it should be possible to even dispense with the
high-order "start" bit, so that more than 128 codes could be
used.  (This could benefit from a faster state machine clock
than 2MHz.)

-michael

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