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Re: Page Boundary Question
"Bryan Parkoff" <spam> writes:
> I think that
> secondary Carry Flag is in 9th bit before NV11DIZC. 9th bit is always
> invisible that it is used for operation.
Here's a description of the internal operation of the 6502 when
executing an instruction like "ADC abs,X". I wrote this up as part
of a thread in another newsgroup, comapring the 6502 to a hypothetical
big-endian version to show why the 6502 being little-endian makes it
faster. Here I've edited out the portions relating to that hypothetical
big-endian processor.
------
When an opcode is fetched, the PC is being incremented and the next
cycle will *always* read the byte after the opcode. There is no delay
while the part decodes the opcode to determine whether it needs the next
byte. I've shown separately what happens "during" a cycle from the
actions that occur on a clock edge. The control signals for the
"during" actions are decoded from flip-flops in the state machine, so
the actions are determined at the previous clock edge. I'm using "->"
to indicate that something drives a bus, and ":=" to indicate that a
register (on the left side of the symbol) is loaded with a value (from
the right side). I'm designating some internal temporary registers as
temp (16-bit, composed of temp_l and temp_h), data (8-bit), and flag
(1-bit). There is a dedicated 16-bit incrementer on the PC, whose
output is called pc_bus. The ALU is simplified to be an 8-bit adder
with inputs alu_a, alu_b (both 8 bits), alu_ci (carry in, one bit), and
result to alu_r (8-bit) and alu_co (1 bit carry out). Note that in
cycle 1, the last part of the previous instruction will be completed,
but that is not shown here. The last cycle of the instruction is really
cycle 1 of the next instruction, so the instruction in question takes
four clocks on the 6502 if there is no page crossing, and five clocks if
there is. These notes have been hastily edited down from the design
notes for a 6502-compatible core, and it's quite possible that I've made
some mistakes in the editing.
I am not privy to the internal details of any of the commerical 6502
microprocessors or derivatives. This is therefore at least slightly
speculative regarding those, but is fairly well supported by the
published data sheet, hardware manual, and programming manual.
cycle little endian 6502
----- ------------------
1. PC -> address_bus
mem [PC] -> data_bus
(opcode)
PC + 1 -> pc_bus
_
_/ IR := data_bus
PC := pc_bus
2. PC -> address_bus
mem [PC] -> data_bus
(LSB of abs. addr)
PC + 1 -> pc_bus
instruction decode
_
_/ temp_l := data_bus
PC := pc_bus
3. PC -> address_bus
mem [PC] -> data_bus
(LSB of abs. addr)
PC + 1 -> pc_bus
temp_l -> alu_a
index -> alu_b
0 -> alu_ci
_
_/ temp_h := data_bus
temp_l := alu_r
flag := alu_co
PC := pc_bus
4. temp -> address_bus
mem [temp] -> data_bus
(operand)
PC -> pc_bus
temp_h -> alu_a
0 -> alu_b
flag -> alu_ci
_
_/ data := data_bus
temp_h := alu_r
PC := pc_bus
if (flag)
go to step N1
5. temp -> address_bus
mem [temp] -> data_bus
(operand)
PC -> pc_bus
_
_/ data := data_bus
PC := pc_bus
N1. PC -> address_bus
mem [PC] -> data_bus
(next opcode)
PC + 1 -> pc_bus
accumulator -> alu_a
data -> alu_b
carry_flag -> alu_ci
_
_/ IR := data_bus
acculumator := alu_r
carry_flag := alu_co
PC := pc_bus