Decimal Flag Question

["Bryan Parkoff" <spam>]

    I reviewed NMOS 6502 and CMOS 65C02 Datasheet Reference.  I only receive
CMOS 65C02 from Western Design Center.
    I show that decimal must be added one extra cycle if it is in BCD mode
on 65C02 Datasheet, but it does not show on 6502.  Is it normal that 6502
does not have one extra cycle?  Why do 65C02 need one extra cycle?  It does
not make sense that 65816 does not have one extra cycle for BCD mode.
Please explain.
    CMOS 65C02 shows that Direct Page Indexed X and Direct Page Indexed Y
must have one extra cycle if it acrosses page boundaries.  In fact is that
it is not supposed to add one extra cycle because it can only access from
$00 to $FF as first page.  Only Absolute Indexed X and Absolute Indexed Y
can add one extra cycle.  Do you think that CMOS 65C02 Datasheet Reference
may contain errors from WDC?  Please advise.

Bryan Parkoff