Re: 14MHz Osc Chip Question

[mjmahon@aol.com (Michael J. Mahon)]

Bryan Parkoff asked:

>    All Apple II, II+, //e, and //c use 14MHz osc chip.  I understand that
>it is only 14MHz that it can divide into 7MHz, 3.5MHz, 2MHz, and 1MHz.  1MHz
>can be used for 6502 CPU only.
>    My question is: If 14MHz osc chip is replaced to 25MHz osc chip, will
>14MHz, 7MHz, 3.5MHz AND 2MHz be REMAINED THE SAME for RAM, Video Scanner,
>Video Monitor, and ETC, BUT 10MHz will be REPLACED from 1MHz for 6502 CPU to
>increase the speed?  Correct?

No.  In general, if you increase the speed of the master clock oscillator,
all the derived frequencies will be increased proportionally, which will be
a problem for the video signal, as you can imagine.

>    (For 1MHz only) I understand that approx 17000 cycles can be executed
>every one second.  I suspect that it is approx 10 to 16 opcode instructions
>can be executed each one second WHILE approx 16500 cycles are TAKEN for RAM
>and Video Generator.  I am confused that only million opcode instructions
>can be executed each one second that is opposite to 12-16 opcode
>instructions.  Can you please explain more.  If it is the case that 1/65
>cycle can be done with opcode instruction each one second while 64/65 cycles
>can be done with RAM and Video Generator.

You misunderstand.

The video generator operates independently of the processor in an
Apple II.  Part of the genius of the design is that the 6502 only accesses
memory during one phase of the approximately 1MHz clock, and the
video generator uses the memory during the other phase.  Not only
does the video access not interfere in any way with the processor
accesses, but the pattern of video accesses serves to refresh the
DRAM without any dedicated refresh circuitry or cycles.

There is a slightly stretched clock pulse every 65 cycles (one
horizontal line time), which serves to alternate the phase of the
3.58MHz color burst from line-to-line, as required by NTSC
standards.  Although this introduces a slight jitter into processor
timing loops, for most practical purposes it can be ignored.

In each second, approximately 1 million processor cycles (and
memory cycles) are available to run instructions.  In the same
time, the video generator accesses memory approximately 1
million times.  The memory actually cycles at approximately 2MHz.

A typical 6502 instruction takes about 3 cycles on the average.
(They range in cycle counts from 2 to 7, depending on complexity.)

>    I am happy that I won on eBay to purchase the Understanding the Apple II
>manual and Understanding the Apple //e manual.  They do provide the
>information about timing scheme.  I am not sure that I understand what the
>manual meant.  I hope that David can be able to tell more on the newsgroups.

You have the definitive documentation of Apple II timing.  It's worth
some study.  Just getting "the answers" will not provide nearly the
same level of understanding that is available by careful study of the
timing generator design, and the reasons for the choices (many of
them dictated by NTSC color video standards).

-michael

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