Request Info on CYA aka FPI chip in IIgs

[noone@nowhere.net]

Helo:
Does anyone out there have schematics and/or timing diagrams and/or 
logic table of the CYA/FPI chip in the Apple IIgs?

(Further referenced as CYA and assuming a Rom3 IIgs.)

Also can anyone tell me if the demultiplexed signal from the CYA chip 
are LSB to MSB compliant with the address bus?  I want to bypass the CYA 
chip to access memory directly from the CPU (at higher speed) except in 
DMA mode.

Is the bank register ($c037) in the CYA or is it somewhere accessible?

I am looking for this information to build a q&d accelerator.  The 
sticky point for me is when to swap in my clock and then synchronize it 
to PH2 when not doing CPU memory R/W.  I assume I will have to mimic the 
functionality of the CYA chip to know when it can accelerate and when to 
slow down.

I have the hardware reference book for the IIgs, 2nd edition but it says 
nothing about the CYA chip's timing and little about its logical 
function.  Most is presumed and and gleaned from postings to CSA2 groups.

Here's my plan.
Solder a socket on a board, place the socket over the CYA chip to grab 
the signals.  Run those signals to a fast CPU and 4M (s)Ram on this 
daughter board.  (Pull main CPU to remove possible bus contention.) 
Derive appropriate clock speed from 14M and supply to CPU whenever in 
1-5M area and in Fast Mode (High bit $c036).  Synch with main board PH2 
when accessing first meg or Mega 2 active or Rom active.

Alternately, for a moderate increase, derive clock from 14M clock and 
swap in when doing internal processing when VDA and VPA both are low.

Any thoughts?

Any hints?

Any suggestions?

Thankx,
Ed
eeastmanNO@SPAMapple2.com