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Re: 6809 mill clone

On Mon, 6 Aug 2012, Alex Freed wrote:


On 8/6/2012 3:12 PM, Steven Hirsch wrote:


Boisy is most definitely the right person to ask about the intricacies
of OS-9/NitrOS-9 and 6809/6309 assembly programming.  He's forgotten
more about it than I'll ever hope to know.

I'd love to see a minimum of 512k on such a card, and it goes without
saying that I want one :-).



I agree, the same way as my PCPI clone takes either 128K or 512K chips.
One question is how to implement the memory management. There seems to be a standard in the 6809 world where the space at $FF00 (?) contains 16 write-only registers that map logical 4K blocks to arbitrary physical memory. That would require a lot more resources to implement than is available in simple CPLDs easy to hand solder. Another extreme is a single 32K block mappable to physical RAM. I wonder what is the minimum for OS9 level 2? I guess reading the CoCo 3 manual may help.
If you're not going to use more than 64K of RAM, you might as well just use Level I. There are probably some other advantages to Level II, but the key thing was that you could use more RAM. Level II needs the memory management.
On the other hand, the SWTP 6809 implemented memory management by putting RAM on the highest bits of the address bus, I think they used 7489s which were small blocks of RAM 4 bits wide (I may not remember the details properly). By feeding data into the RAM, it controlled the output. I'm sure information can be had. Jim Stark had a long running series on the SWTP computers in Kilobaud (maybe it had turned to "Microcomputing" by then), which was more like a column, and he covered that memory management at one point. It at least provides the concept of what's needed. 

   Michael