Re: Determining amount of RAM on a board?

[dempson@actrix.gen.nz (David Empson)]

Ernest <ernestls@home.com> wrote:

> "David Empson" <dempson@actrix.gen.nz> wrote in message
> 1eydwbq.1rmzydw1lx7l6oN%dempson@actrix.gen.nz">news:1eydwbq.1rmzydw1lx7l6oN%dempson@actrix.gen.nz...
> > Ernest <ernestls@home.com> wrote:
> >
> > > "Paul Schlyter" <pausch@saaf.se> wrote in message
> > > news:9ll3m7$b3l$1@merope.saaf.se...
> > > > In article <JXmf7.31513$vW2.13941834@news1.sttln1.wa.home.com>,
> > > > Ernest <ernestls@home.com> wrote:
> > > > >
> > > > >"william strutts" <wrstrutts1@nospam.home.com> wrote in message
> > > > >news:EHmf7.38773$K6.15676876@news2...
> > > > >
> > > > >> Most chips will have something in the line of 44xx or 41xx
> > > > >> The 44 series is 4 bits wide and 41 series is 1 bit wide.
> > > > >> The older computers used for the most part 1 bit wide chips.
> > > > >> 4104  - 4k x 1
> > > > >> 4108 -  8k x 1
> > > > >> 4116  -16k x 1
> > > > >> 4164 - 64k x 1
> > > > >
> > > > >So what would a bank of eight 4164np-20 chips be?
> > > >
> > > > It would be 64K x 8 bits = 64 Kbytes !!!!
> > >
> > > 8 bits to a byte, right so...
> > >
> > > 64,000 divided by 8 = 8000, or 8k bytes per chip... times 8 chips = 64k
> > > bytes.
> >
> > Except that it isn't "8K bytes per chip": it is "one bit from each of
> > 64K bytes per chip".
> 
> Wouldn't that mean that I would need a lot more than 8 chips then, if each
> chip is only one bit?

No, each chip is only one bit WIDE, but it is 65536 bits long - a tall,
thin column, as I said.  The 4164 chip accepts a 16-bit address from the
motherboard and allows a single bit to be read or written at that
address.  You need eight chips to form complete bytes in each memory
location - the same 16-bit address is fed to all eight chips.

> So if 8 chips equal 1 byte, then again, I would need 64 banks of 8 chips,
> right? Obviously that isn't right but I'm a little confused. If each chip
> has 8k bytes, or 65536 bits but you need a row of eight chips for the full
> 64k bytes to work, then I think I understand. Each chip has lots of bits,
> but no bytes are formed unless all 8 chips offer one bit each, at any one
> time.

Yes, that's right (except that it isn't "8k bytes" per chip - just "64k
bits" - you cannot get any number of "bytes" from a single 4164 chip,
because it can only deliver one bit at a time.

> Why did they set it up like this?

To save space, reduce the amount of additional circuitry required, and
to minimise the cost.

The RAM chip actually gets its address supplied as two 8-bit addresses
(a row and column), so the total number of pins required is 8 (address)
+ 2 (column and row strobes) + 2 (read/write and chip select) + 2 (data
in and out) + 2 (power and ground) = 16.  (It might need seperate read
and write enables as well as chip select, so that would make the package
18 pins; I haven't looked at the details recently.)

A 4464 (four bits wide) probably has a bidirectional data bus, so it
only requires two additional pins (if not, it would need six more pins),
but was quite a lot more expensive at the time the early generations of
Apple IIe were being made.  The 4464 was used in the "platinum" model of
the IIe (1986ish).

By comparison, an 8K byte static RAM chip (6264) is 28 pins, and the
package is physically almost four times larger than a 4164.

> Why not just use 8k bytes from each chip, and then move on to the next when
> you need more room? Wouldn't that make diagnostics easier, if you lose a
> chip.

Perhaps, but in additional to having to fit physically larger chips, you
also need to decode the address: instead of being able to provide a
simple 16-bit address to each chip, you need an extra chip which takes
the top three bits and decodes them to form eight chip select signals,
one of which goes to each 8Kx8 RAM (along with the remaining 13 bits of
address, which go to all of them).

With the 1-bit wide or 4-bit wide memories, no additional circuitry is
required - the address and chip select signals are identical for each
chip, and the only difference is which bit from the data bus goes to the
data input and output pins (possibly via a buffer chip).

Besides, they didn't make dynamic RAM in this configuration, and static
RAM was a _lot_ more expensive.