Re: SIMMS for IIgs

[dempson@actrix.gen.nz (David Empson)]

william strutts <wrstrutts1@nospam.home.com> wrote:

> "David Empson" <dempson@actrix.gen.nz> wrote in message
> 1excaqg.1vdar5yf9rjooN%dempson@actrix.gen.nz">news:1excaqg.1vdar5yf9rjooN%dempson@actrix.gen.nz...
> 
> >
> > Most SIMM-based cards only support memory configurations where all SIMMs
> > are the same size, and the number of SIMMs installed is a power of two
> > (1, 2, 4 or 8).  This is how my OctoRAM worked.
> >
> > You have to install the SIMMs in the right order, and cannot use a
> > configuration with three SIMMs.
> 
> I tried it with 4 meg simms in the first two slots but the machine
> displayed garbage on the screen.

You may be lucky that the 4 MB SIMM worked at all.  Apple IIgs
SIMM-based memory expansion cards only support 256 KB and 1 MB SIMMs
(some only support 1 MB), since the motherboard does the address
decoding for DRAM chips (or SIMMs) on the memory expansion card, and it
only supports row sizes of 256 KB or 1 MB.  [See the end of this article
for exceptions.]

I've used an OctoRAM, which has eight slots, supporting 1, 2, 4 or 8
SIMMs.  All of the SIMMs must be the same size (all 256 KB or all 1 MB).
Using this card with all 8 sockets populated may introduce DMA
compatibility problems.  The OctoRAM uses five jumpers to set the
configuration.

I've also seen one other SIMM-based card, which had four sockets and
only supported 1 MB SIMMs (it probably had two DIP switches or jumpers
to set the number of enabled banks).  I forget which brand this was, but
it might have been the Q-Ram.

> It would work with one 4 meg simm but it was reporting the wrong amount of
> memory.

At best, a 4 MB SIMM would appear to the computer as 1 MB, but this
requires all of the following conditions to hold:

- 4 MB SIMMs must have the same pinout as 1 MB, using an extra pin to
provide the additional two bits of the address.  [This seems very
likely.]

- The memory expansion card must have tied this extra address pin to an
appropriate voltage (it doesn't matter if it is grounded or tied to +5V
through a resistor, but it cannot be left floating).  This applies to
all sockets on the card.  [This may or may not have been done on any
particular brand of card.]

- The RAM on used on the 4 MB SIMMs must support the same refresh
mechanisms and page size as a 1 MB SIMM, otherwise the data on the SIMM
may be corrupted.


Regarding memory decoding in the IIgs: most memory expansion cards rely
on the decoding support of the FPI/CYA chip on the motherboard, which
provides correctly multiplexed row and column addresses, with RAS and
CAS signals.  The motherboard also implements the refresh mechanism for
the DRAM on the card, and use of the address signals from the
motherboard is required for DMA compatibility.

Using the motherboard support means that the circuitry on the memory
expansion card is rather simple.  It needs to tie a voltage to a pin on
the slot which tells the motherboard whether to use a row size of 256 KB
or 1 MB (9 or 10 address pins, with multiplexing to get 18 or 20 address
bits).  The card needs to buffer some signals, and if it implements more
than one row of memory, it also has to decode a two-bit row select
signal.

These techniques allow a card to support 1, 2 or 4 rows of memory, i.e.
a card which uses 256 KB rows (like Apple's own card) can support 256
KB, 512 KB or 1 MB; a card with 1 MB rows can support 1, 2 or 4 MB.

To support more than four rows, the card must also decode the bank
address, which is placed on the data bus by the CPU at the start of each
cycle.  The big catch: the bank address is not valid for DMA cycles, so
a card which uses this technique will not be compatible with most I/O
cards which use DMA (the exception being the RamFast, which uses a
special trick to work around this problem, but even then it doesn't
necessarily work with all memory cards).

I did a partial analysis of the OctoRAM's circuit, and I discovered that
it only refers to one bit of the bank address from the data bus, which
is then combined with the normal row select signals to form a three-bit
row select; this is decoded to allow one of eight rows to be selected.

If the OctoRAM is set to use four or fewer rows, then it ignores the
bank address, and will retain full DMA compatibility.  It only risks
incompatibility when eight rows are enabled.


There are other cards which completely ignore the row select signals and
always decode the bank address from the data bus.  These cards can be
more flexible in the memory configurations they support, but they are
much more likely to be incompatible with DMA, and may be tied to a
particular version of the IIgs motherboard (ROM 00/01 or ROM 3) unless a
hardware modification is made, such as replacing a decoding chip such as
a PAL/GAL/PLD, or using a jumper to set the machine type.