Re: A question to David Empson on ZipGS Cache Memory Speeds

[dempson@actrix.gen.nz (David Empson)]

Marvin Miller <marvinmiller@hotmail.com> wrote:

> Hi David !!

Howdy.

> Long, long ago in a galaxy far, far away you posted a message relating
> to ZipGS memory speeds that I've attached below to 'jog the fog' so to
> speak!

Well, that was a long time ago, but I vaguely recall it upon rereading.

> Back then, you made a nice table on ZipGS memory speed requirements &
> oscillator speeds.

> [1] In light of the time that's gone by (and probably increased
> learning) would you say that this table still makes a good 'general'
> guide?

With a caveat: based on a theory of how the Zip cache architecture
worked.  I have never had confirmation of this, so I can't be confident
that the numbers are accurate.

I expect that it is more or less correct, but now I'd be inclined to err
on the side of caution, and get the RAM as fast as possible: preferably
something like 2/F minus a constant.

> [2] If a person bought the fastest possible cache chips (say for a
> 20Mhz //GS) and than ran the Zip at half that speed (say 10Mhz) would
> there be a problem or would it be advantageous to run the processor
> Mhz as near as possible to the reccommended chips?

I wouldn't expect any problems with the RAM being too fast.

Having said that, we have encountered a problem in this area at work,
with one of our older circuits: it works fine with a 120 ns or 150 ns
static RAM, but fails if a 70 ns RAM is used.  The product is several
years old and has been superseded twice, so we just avoid the problem
and haven't investigated it in detail.

In this case it is probably a race condition due to a multiplexed
address and data bus, and a probable design fault that is only exposed
if the RAM produces read data too quickly.

> Here's a more complete table based on your long ago theories;
> 
> 
>   CPU    Oscillator  ------- DATA RAM speed ----------TAG RAM Speed
>  Freq.   Freq. (F)   min (2/F)  max (3/F)  est (2.5/F)     (3/F -30ns)
> 
>  7 MHz    28 MHz      71.4 ns     107 ns      89.2 ns     77.1ns
>  8 MHz    32 MHz      62.5 ns     93.0 ns     78.1 ns     63.7ns
>  9 MHz    36 MHz      55.5 ns     83.0 ns     69.4 ns     53.3ns
> 10 MHz   40 MHz      50.0 ns     75.0 ns     62.5 ns     45.0ns
> 11MHz    44 MHz      45.4 ns     68.1ns      56.8 ns     38.1ns
> 12 MHz   48 MHz      41.6 ns     62.5 ns     52.0 ns     32.5ns
> 13Mhz     52 MHz     38.4 ns      57.6 ns     48.0 ns     27.6ns
> 14 MHz   56 MHz     35.7 ns      53.5 ns     44.6 ns     23.5ns
> 15MHz    60 MHz     33.3 ns      50.0 ns     41.6 ns     20.0ns
> 16 MHz   64 MHz     31.2 ns      46.8 ns     39.0 ns     16.8ns
> 17MHz    68 MHz     29.4 ns      44.1 ns     36.7 ns     14.1ns
> 18MHz    72 MHz     27.7 ns      41.6 ns     34.7 ns     11.6ns
> 19MHz    76 MHz     26.3 ns      39.4 ns     32.8 ns      9.4ns
> 20MHz    80 MHz     25.0 ns      37.5 ns     31.2 ns      7.5ns
> 21MHz    84 MHz     23.8 ns      35.7 ns     29.7 ns      5.7ns
> 22MHz    88 MHz     22.7 ns      34.0 ns     28.4 ns      4.0ns
> 23MHz    92 MHz     21.7 ns      32.6 ns     27.1 ns      2.6ns
> 24MHz    96 MHz     20.8 ns      31.2 ns     26.0 ns      1.2ns
> 25MHz   100MHz     20.0 ns      30.0 ns     25.0 ns      0.0ns

Of course anything above 20 MHz is pure speculation - the ASIC is only
rated at 20 MHz, and the CPU is theoretically rated at 14 MHz (though
most appear to have been able to operate as fast as 20 MHz).  Has anyone
succeeded in getting a ZipGS working faster than 16 MHz?

Where did you get the (3/F - 30 ns) formula for the tag RAM?  As noted
in my original post, I've seen a 9 MHz ZipGS supplied with 70 ns tag and
data RAM, which is way over your 53.3 ns figure (though it could have
been hand-picked RAM which was actually faster than this).

Just to confuse things, my 8 MHz ZipGS was supplied with 45 ns RAM.