Re: Apple II Bus Timing

[dempson@actrix.gen.nz (David Empson)]

Matthew T. Russotto <russotto@wanda.vf.pond.com> wrote:

> In article <1eiv0g3.1t3jn7y1vlmxz4N%dempson@actrix.gen.nz>,
> David Empson <dempson@actrix.gen.nz> wrote:
> 
> }The bus Phi0 and Phi1 signals are generated by timing ciricuitry on the
> }motherboard.  In the IIe, the 6502 or 65C02 Phi0 input is driven from an
> }inverted copy of the Phi1 signal.
> }
> }Just to confuse things, it looks like the IIe actually uses an inverted
> }copy of Phi1 to drive the Phi0 input to the 6502.  I can't see any
> }indication that Phi1 is even provided to the CPU, but this might be an
> }error in the circuit diagram.
> 
> Phi1 is an output, I think.

Whoops - I forgot to delete that sentence during editing.  (I thought it
was an input when I started writing the post, and discovered it wasn't
while checking some other details.)