Apple II Bus Timing

["Andrew Quinn" <andrew.q@ihug.co.nz>]

I have been puzzling over some strange timing related issues on my IDE
controller board for some time and while at the local surplus electronics
store picked up a book called "The Apple II Circuit Description" by Winston
Gayler.  In this book I find a caution for designers that basically says:

"The 6502 data sheet specifies that at the end of a read cycle the data must
remain stable on the 6502 inputs for a 10ns hold time after the 6502 o2
clock falls."

The apple bus provides o0 (rather than o2) for bus timing and this appears
to lead o2 due in the timing diagrams but I cannot find timing details of
this lead so I can hold the data on the bus a little longer.

Does anyone have any ideas?

Regards...... Andrew