Re: Apple II Bus Timing

[Rubywand <rubywand@swbell.net>]

Andrew Quinn writes ...
> 
> I have been puzzling over some strange timing related issues on my IDE
> controller board for some time and while at the local surplus electronics
> store picked up a book called "The Apple II Circuit Description" by
> Winston
> Gayler.  In this book I find a caution for designers that basically says:
> 
> "The 6502 data sheet specifies that at the end of a read cycle the data
> must
> remain stable on the 6502 inputs for a 10ns hold time after the 6502 o2
> clock falls."
> 
> The apple bus provides o0 (rather than o2) for bus timing and this appears
> to lead o2 due in the timing diagrams but I cannot find timing details of
> this lead so I can hold the data on the bus a little longer.
> 
> Does anyone have any ideas?
> 
 ....

     At least in the Apple II Reference Manual (for II and II+), Apple is
fairly free with its use of signal names. The signal Apple calls "o0" can be
taken as equivalent to "System o2" as used in some 6502 hardware references.
(Apple even mentions that their o0 is equivalent to the usual o2 somewhere in
the manual.)

     Apple uses an external oscillator and dividers to obtain its o0 (which
it sends through a TTL gate to the 6502 "o0" input pin).  So Apple's o0 is
going to be a bit different from o2 as it would normally come from the 6502
"o2" pin plus a couple TTL gates; but, evidently, Apple's o0 is close enough.

     You probably do not need to worry much about the Data Hold time (TH)
parm. Apple's o0 seems to be symmetrical and may give you a slightly
stretched version of o2. Besides, about the only place you might even have a
chance of turning off data before TH after o2 is the data bus buffers and
that looks pretty unlikely.



Rubywand