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Re: Modern A2 successor

Arkain <rwking@no.usa.spam.net> wrote:
> The price? Probably astronomical for a uP while not so high for a common IC.
> This is why I'm thinking of using a high-speed risk processor and a custom
> translator so that the uP appears to be reading the enhanced 65xxx language.
> If I can find a way to make a uP (relatively)cheap, I'll go that route.

If you could find a good engineer, you could implement the ill-fated 65C832
in VHDL or Verilog, and it'd probably be small enough to fit on relatively
cheap FPGA's.

On the right PGA you could run the chip at up to 100Mhz, and you'd have
65C02/65816 compatability.

I think that'd satisfy everyones requirements.

Cheers,

Matt

-- 
              Matt(hew) Jenkins. Computer Science (RMIT Bundoora)
                           email: mdj@cs.rmit.edu.au
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