Re: Applesoft I and II and floating-point performance

[pausch@saafNOSPAM.se (Paul Schlyter)]

In article <zR_R4.65$sB2.481@newsfeed.slurp.net>,
Forrest <bctimes@hotmail.com> wrote:
 
>Somewhere, pausch@saafNOSPAM.se (Paul Schlyter) wrote:
>> Applesoft II also kept
>>the floating-point performance of Applesoft I, which appears to have
>>been less lousy: the only Applesoft patches I've seen which attempted
>>to speed up the floating-point performance used coprocessors of one
>>kind or another.  I tested one myself, which used the ALF 8088
>>coprocessor card: using this card + the accompanying patch would
>>speed up the floating-point in Applesoft by a factor of about 3 to 5.
>
> Poking around I found this:
>
> http://people.delphi.com/paulrsm/68k/dg/dg12.htm
>
> which contains some comments regarding the ALF 8088 by some people
> behind 68000 based boards of the same function.
>
> The interesting bit is how impressive the numbers aren't.
>
> The idea is to optimize performance by using Microsoft TASC
> to wipe out the Applesoft interpretive overhead, and then
> patch out the calls to the Applesoft FP routines.  And yes,
> everything beats the Applesoft version by as much as a factor of 6
> (or even 50* when they substitute their own custom language).
>
> Thing is, they're comparing the 1 MHz Apple to systems running
> considerably faster.  Is it impressive to beat the II by a factor of
> 6 when running at 8 or 12 times the clock rate?  Especially when
> using a processor that should be _more_ powerful, cycle for cycle, 
> proportionately speaking?
 
Well, the ALF 8088 board ran at 5 MHz, not 8-12 MHz.  It was
sometimes advertised as "the card IBM doesn't want you to buy",
referring to that it was faster (5 MHz) than the then newly released
IBM PC (4.77 MHz).
 
The biggest speedup probably came from using the built-in (integer)
multiply instruction in the 8088 -- but that instruction wasn't
particularly fast, requiring some 100 clock cycles: it was implemented
as microcode.  In the 80188 the integer multiply was implemented in
hardware instead, resulting in a speedup of a factor of about 3: now
it required only some 30 clock cycles.
 
> Looks to me people would've been better off with accelerator boards.
>
> (* Slow their 68000 to 1 MHz and it's more like 4.  I think
> we're in the realm of potential optimization here.)
 
-- 
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