Re: IIgs Accelerator Project

[supertimer@aol.com (Supertimer)]

Frank Carney <frankcTAKETHISOUT@ANDTHISALSOsrv.net> wrote:

>Well, I have decided to start slow.  
>
>I am working on building an 8088 system (I have the chips breadboarded
>and wiring has begun).  Once I get up to speed on the design of 8088
>systems and programming them I will release a block diagram of it.  From
>there I will start writing code and experimenting with interfacing to
>the Apple IIgs hardware.  From that point I will write a IIgs emulator
>in assembler and will need input from people who have written emulators
>of the IIgs.  Then I will move to a larger processor such as the 386.  I
>should be able to use all the code designed for the 8088 if I run the
>386 in real mode.  From there the next step would be to rewrite the
>accelerator in protected mode and add more memory.  Finally, from this
>point on I guess the next step would be to go to high speed chips of the
>486, 586, 686 and beyond!

So are looking to design something like a Pentium or K6-2 sitting
on a small circuit board connected to a small bit of RAM and ROM
and cache RAM with a program in ROM emulating a 65C816 and
have the whole "ZipChip" type device plugged into the IIGS
motherboard.  Sounds great to me.

I recommend using a 256k cache.  That should take care of any
concerns about bus slowdown since you are likely to see speed
increase at hundreds of Mhz with that much cache.

Interfacing with the motherboard will provide bullet-proof hardware
and software compatibility.  You can even run VOC on it.