Re: 65c02 VHDL model

[Rubywand <rubywand@swbell.net>]

Phoenyx writes ...
> 
> "Scott L. Baker" wrote:
> >
> > Hello,
> >
> > I wrote a 65c02 VHDL model that I programmed into an Altera 10k30 FPGA.
> > I have booted Apple DOS and played Frogger.  Write to me or visit
> > my web page for details.
> >
> >               Scott L. Baker            scd@teleport.com
> >               Sierra Circuit Design   www.teleport.com/~scd
> 
> Hi Scott,
> 
> Thanks for the link. I will read the info you have provided
> and will get back to you with more questions.
> 
> First though, can this be done with the 65816 and 65802? And
> how cost effective would this be? Finally, can the ROM be
> put on the chip, provided a legal version can be provided?
 ....

     Sierra Circuit Design's site at http://www.teleport.com/~scd/ is quite a
goldmine of information about chip design. (It's been added to the FAQs
'Major Sites' links.)

     According to the the overview report on Scott's 65C02 design, it was
implemented in the Altera 10K30 Field Programmable Gate Array and checked out
running as the microprocessor in an Apple IIe.

     The same report mentions speeds of the kind we would want for a new
65C816 (or bigger 65xxxx) design:

 ....
>>
All state transitions occur on the falling edge of 
this clock, so precise clock symmetry is not required.
Your exact system clock rate will depend on your
synthesis tools and memory access time, but in a
modern CMOS process technology, system clock
rates of 50 to 100 MHz should be easily achievable.
<< 

     An 80MHz 65C816 with added address-relative JSR instructions would be a
very nice core for a new IIgs expansion.



Rubywand