Problems in Modernizing a IIgs, con't

[bjblackbear@ibm.net (B.J. Major)]

Subject:     Re: Fwd: Re: Problems in Modernizing a IIgs, con't
Sent:        10/25/97 2:08 AM
Received:    10/24/97 5:14 PM
From:        Lewin A.R.W. Edwards, sysadm@zws.com               

>> Also, consider that one of the WORST features of the P6 is its
backwards
>> compatibility. That's backwards compatibility spelled "Backwards.
>
>     For sure, after a decade, we are talking about something more than
>an upgrade. Backward compatibility is the sort of thing you handle by
>offering a plug-in card.

Well, gee now, this would be a plug-in card exactly like the LC-PDS card
Apple offered for Apple II compatibility?

>We would want the uP and motherboard of any new
>II to aim for performance vis-a-vis the PC competition.

Which means PCI bus and a 64-bit MPU, L2 and backside caches which means
you already have a commitment to build something that's 95% a Macintosh
anyway.

>    Still, do not be too concerned about Intel's future. Today's RISC
>becomes tomorrow's CISC. An integrated, optimized design will
>out-perform the more generalized hardware it integrates and optimizes.

There is absolutely no way that the x86 can "integrate or optimize" 
anything to make it better than what it is. MP Intel beasts are a waste
of money, and SMP or other MP technology is the way of the present and 
future as far as enhanced computing power goes.

>    The difference in computing power between the workstation and the PC
>shrinks with each new generation as does the time between generations.

Er... what universe would this be in, then? I'm sorry (shuffling through
catalog...) no, I didn't think so - maybe the page is missing, but I 
can't seem to find any Intel-based machine running at 600MHz with a 
one-or-two-cycles-per-instruction instruction set and a high-performance
optimizing compiler. Face it, P6 is just a fast 8086. MMX was the
biggest 
non-event of the 1990s, even more so than Windows 98 will be (if it's 
ever released).

>> Nope, not even vaguely (have you ever programmed the 680x0?).
Consider
>> the addressing modes offered on the two CPUs and consider how many
>
>     Okay; the 68xxx and 80x86 have bigger, more 'powerful' instruction

The x86's instruction set and register space is not VASTLY larger or
more 
powerful than the 6502's, and suffers from some of the same silly 
restrictions, where "general-purpose" registers aren't, and certain 
operations can only be performed on certain registers when the phase of
the moon is favorable.

The 68000's instruction set is substantially better designed (it
inherits 
from the 6809, which inherits from the DEC LSI-11 processors, 
apparently... or so I'm told - certainly, they "feel" related). It is 
impossible to write a highly optimizing compiler for the x86, which
means 
the ONLY way to get maximum performance out of the damn thing is to
write 
your programs in asm. Since no major programs are written in asm any 
more, and OS vendors are encouraging developers to write even device 
drivers in C++ or similar, this means that you will never get the same 
slice of your CPU's potential performance on an x86 as you did on a 68k
- 
or a well-designed RISC platform.

>etc.). When it comes to 'getting things done', the 65xxx has several of
>the advantages normally associated with RISC. At same base oscillator
>frequencies, a 65xxx design will simply 'mop the floor' with a 68xxx or
>80x86.    

You still haven't shown any quantitative empirical evidence of that. 
Unless you are talking about putting a 4.77MHz 8088 up against a 32MHz 
65832.

>> Also consider that the 65xxx series uses zero page as basically an
extra
>> register store, and all indirect addressing modes go through pointers
in
>> ZP. This is torture for a multitasking OS, having to juggle pointers
>> through ZP and maintain ZP contexts for each process.
>
>     No problem. An enhanced 65xxx design could have many 'Zero page'
>banks.

To quote Daneel from The Naked Sun, "Partner Elijah, it seems obvious 
that you are constructing this line of reasoning without really
believing 
it". The 6502 is almost the ultimate von Neumann architecture, the only
things which aren't on the main storage bus are A, PC, X, Y and F. You 
know what zero page really is? It's 256 single-octet REGISTERS which
they 
didn't have room to put on the MPU's die. Putting CPU register space
into 
main memory was a great Cunning Trick(sm) back in the days when we all 
ran at 1MHz, but these days (a) die space is cheap, and (b) main memory
access is a serious bottleneck. In fact, we are heading more towards 
Harvard-architecture machines which have separate program and data 
address spaces, to reduce contention. Indirect addressing modes which 
require main memory access to fetch the address are just not part of the
Real World today. An MPU or MCU which has indirect memory access through
internal registers will, clock for clock, and even with instruction 
timings being identical, execute indirect memory accesses in at least
1/2 
the time of the 65xxx. When talking about really fast MPUs that have 
internal clock multiplication (which is to say, all of them used in GP 
consumer computers today), that's probably closer to 1/8th or 1/10th.

>> Absolutely NOT. Apple was never anything more than a minor consumer
of
>> 680x0 chips. 68000s and 68010s in particular are used widely in
embedded
>
>     These examples all seem to be post-Mac. Scott's point is that

The 68000 was in widespread use in embedded systems and minicomputers
way 
before the Macintosh was anything more than a gleam in Apple's eye, and
I 
would be very surprised indeed if all the Apple machines put together 
totaled more than two or three percent of total 680x0 sales. You could 
infer a lot from the sales figures for different package types, if you 
got them out of Motorola. Apple only ever used the big 64-pin DIP
plastic 
package 68000P8 in Macs; many embedded solutions use the faster P10 or 
P12 variants, and/or PLCC or SOIC/SSOP package devices.

>     True. As long as Apple leadership was too short-sighted to
>recognize the need for a next-generation 65xxx by 1982, they were stuck

There was no need for a next-generation 65xxx. There was simply need for
a faster MPU, and they had the choice to spend millions in developing 
what would, basically, be a custom chip for Apple alone, or to buy an 
off-the-shelf high-performance MPU with excellent development tools, 
multiple sources (Motorola, Hitachi, SGS-Thompson, Signetics) and a huge
existing userbase.

>non-65xxx, non-II platform did produced a short-term success. In the
>longer term, it was very likely a fatal mistake.

Yeah, right. And the entire reason Digital Research vanished is because
they didn't do a version of CP/M optimized for the processor which would
have come after the RCA 1802 if anybody had actually used this chip 
enough to want a next generation. How could they have been so blind?


=== From the Apple PowerBook of ======================
Lewin A.R.W. Edwards [Team OS/2] <http://www.zws.com/>
Programmer + Hardware Eng     Certified Apple Engineer
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=== (C) Copyright 1997 by Lewin A.R.W. Edwards =======