Re: Zip GS questions

[pubpc1@library.ucla.edu]

pubpc1@library.ucla.edu wrote:
>eddy@cs.ucdavis.edu (arekusu) wrote:
>>Paul Schultz (pschultz@med.wayne.edu) wrote:
>>: Check out the FAQ. It will fill in any gaps in the above info that
>>: you will need to do the cache upgrade.
>>
>>A questions I have about Zip upgrades, not in the FAQ:
>>
>>How do you know if the ASIC will handle speeds greater than ~12 Mhz?
>>
>>I can't push my 1.02 board past 10Mhz, with 64k of 15ns SRAMs w/ or
>>w/o the high speed 740x chips.
>
>When you put 15ns SRAMs into both TAG and CACHE, the Zip becomes very
>unstable.  What you have to do is put the 15ns SRAMs into the TAG
>sockets and put slower (45ns or even greater, but not TOO slow) SRAMs
>into the CACHE sockets.  Try your original chips for the CACHE sockets
>and see if it will work.
>
>I have mine working at 13.75MHz with 15ns in CACHE and 45ns in TAG,
                                      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>but I had to set the DIP config to think there was 16K of cache even
>though the Zip has 64K.  I did not need to replace the 7400.


That was a typo.  I meant to say 15ns in the TAG sockets and 45ns
in the DATA cache sockets.

15ns is too fast for both, so slower ones have to go into the
data cache.

:)

-Scott G.