Re: Why/how does Zip 6502 work?

[nathan@visi.com (Nathan Mates)]

In article <4v05lk$fp4@balsam.unca.edu>,
Rhonda K. Faircloth <RKFAIRCLOTH@unca.edu> wrote:
>I read a few things about the 14mhz 65816 and that raises questions for me.
>The Apple //e and //gs both have the motherboard speeds hardwired. This
>is why the Zip gs needs to be on a card rather than simply replacing
>the cpu in socket. However, the Zip 6502 for the //e doesn't need to be
>on a card, it simply replaces the normal 6502.

   Earlier accelerators for the //e were on cards. Then Zip
Technologies (later MCTA) figured out how to combine all the logic
onto one package that was the same pin size as the 6502, but was
thicker. Basically, in the extra volume that a 'tall' 65C02 had, they
put a small amount of cache, control logic, and stuff to talk to the
1MHz motherboard. In short, the Zip Chip is a very compact board.

   Nobody's managed to replicate the same stunt for the GS. Early Zip
GS advertisements sorta hinted at an unexpandable "miniboard" Zip GS
accelerator (plugged into the processor slot, but was larger than the
processor slot, and would hopefully fit under cards in the various
slots). That never made it out the door, only the card version.

>I think I have an answer,
>can anybody verify this? I know that the 6502 requires more than one
>clock cycle to perform an instruction, sometimes 5 cycles. Is the
>Zip 6502 able to do it's instructions in less cycles, perhaps only 1
>at it's highest speed? Am I even close?

   Not at all. The biggest reason why instructions take a number of
clock cycles is that the processor needs one clock cycle per byte
transferred to/from memory, as well as ones for math and the
like. That includes opcode fetching, operand fetching (a 3 byte
instruction thus has a minimum of 3 clock cycles to be read into the
processor), and the time needed to execute it. That limit is imposed
by the 8-bit data pathway to the processor, and the 1 clock cycle
memory fetch of the 65xx.

   How you can run at higher speeds with a faster processor is by
having some amount of ram that doesn't take a 1Mhz Clock Cycle to read
in a byte.  I believe the Transwarp //e had 128K on it that it could
access quickly. Replicating 100% of the memory at a fast speed is usually
expensive when most programs tend to have a central core that's run
all the time, and other things aren't accessed very often at all.

   Cache ram (I believe the ZipChip had 8 or 16K of it) does just
that-- it keeps around some of the most recently accessed ram in hopes
that it'll be accessed again. If a memory request can be serviced from
cache, great. If not, slow down to 1Mhz and grab it off the memory
bus. Cache ram isn't perfect (if your program and/or data is larger
than cache, it can be pretty much useless), but it works often enough
in computers that it's pretty much become standard in the last few
years.

Nathan Mates



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<*> Nathan Mates http://www.visi.com/~nathan/      <*>
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