"Michael J. Mahon" <mjmahon@aol.com> wrote in message
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Charlie wrote:
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"Michael J. Mahon" <mjmahon@aol.com> wrote in message
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Charlie wrote:
"Charlie" <charlieDOTd@verEYEzon.net> wrote in message
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"Michael J. Mahon" <mjmahon@aol.com> wrote in message
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rich12345 wrote:
On May 22, 12:28 pm, "Charlie" <charlieD...@verEYEzon.net>
wrote:
I'm having trouble getting my mind wrapped around this
statement.
Could you clarify it? Specifically why is it necessary to
access
both the AUX memory and main memory in the same cycle?
AUX RAM and MAIN RAM need to be accessed in the same cycle
for 80 column text and DHGR graphics.
1/2 of the video data is in MAIN, the other 1/2 is in AUX.
Same cycle: It takes 2X the time to display 80 columns
compared
to 40 columns. It takes 2X the time to display DHGR
compared to
HGR....
Actually, it takes 2x the number of *bits*, in exactly the
same time
(1 cycle), so the need to access both main and AUX memory
concurrently.
Only one address bus is needed, but two data busses are
required.
If you access AUX at a later cycle, then you add to the
time to
update/refresh the video output.
(maybe?)
Very close. ;-)
My reason for asking is that I've been trying (without much
success) to get DHR working on the Carte Blanche card. If it
is impossible I'll feel really good when I achieve it :-)
Anyway, because of my lack of success, I've been trying to
learn more about how DHR works. That's why I am concerned
about your statement. If all the DHR video data doesn't
appear on the peripheral slot bus I'm in deep trouble.
Not being a hardware guy I figured that if data from the AUX
memory and main memory were placed on the peripheral bus
sequentially but interleaved then the it must have been
accessed that way (not concurrently).
The CB card does *seem* to pick 80 column data off the
peripheral bus so I figured it could do DHR as well. Am I
wrong?
To maybe answer my own question: I suppose the CB card is
picking up the writes that a program is making to the video
memory and using that to generate the VGA output. If that is
the case then I needn't be concerned with the concurrent
accesses to AUX memory and main memory.
Bingo!
The problem with DHR on the CB is then having enough RAM to
buffer
both the main and the AUX hires screen areas, 16KB in total.
80-column text is easier, since only 2KB of buffer is required.
That is true Michael, but I don't thing the CB card is buffering
more than one line at a time, however, Charlie will need to
verify that for us.
The CB has 256KB of SRAM on the board and buffers all the video
as it appears on the peripheral slot bus. In fact it buffers the
video data in exactly the same addresses as it would be on a //e.
That sounds like plenty of RAM!
Steve and Alex wisely added extra RAM on the board.
For some reason--ah, the discussion about expanding the character
ROM
for the CB's VGA display--I suspected that memory was in short
supply.
So it seems that only ROM is in short supply. ;-)
Yes, there isn't much RAM on the FPGA itself and in fact when I
added the 1KB for mousetext characters it used up what was left :-(
In that case, upgrading JAT to do DHR should be quite doable, by
mirroring both main and AUX display buffers and by changing the
video scanner. Tracking all the bank switches may already be
there...
That's what I've been working on. I'm sure my problems are mainly
with my lack of understanding of hardware in general and in Verilog
where I'm still taking baby steps.