Re: ZipGS more stable with slower SRAMS?

[dempson@actrix.gen.nz (David Empson)]

In article <4sld4m$8bm@nyx10.cs.du.edu>, wbaguhn@nyx10.cs.du.edu (Will
Baguhn) wrote:

>The only possible reason to maybe use slower chips in the DATA sockets
>is that (some well-knowing hardware guru want to confirm this?) I think
>they use a little less power, and that becomes an issue at higher speeds
>with the stock power supply and motherboard.

Yes, that could happen.  It is hard to tell without measuring the chips in
question, but if you read the data sheets for RAMs, the faster ones
generally require more current.

However, this might just be a reflection of the test conditions.

In most cases, CMOS-based logic chips consume more current for higher
clock speeds (there is quite often a linear relationship between clock
speed and current consumption).  The reason for this is that CMOS gates
only consume an appreciable amount of current when they switch states, not
when they remain stable.  The faster you switch them, the more current
they consume.

In the case of static RAMs, the data sheets indicate typical and maximum
power consumption for at least one access speed, probably the rated speed
of the chip.  If you compare the columns for chips rated at different
speeds, the faster ones (which are being tested at a faster speed) consume
more current.  The data sheets don't often say anything about current
consumption if the chip is run at a slower speed.

It is quite likely that if you run the faster chips at a slower speed,
then they will consume a similar amount of current to the slower chip
(possibly a little more, possibly a little less - it depends on the
particular chip).

-- 
David Empson
dempson@actrix.gen.nz
Snail Mail: P.O. Box 27-103, Wellington, NEW ZEALAND