Re: Senior Prom logic

[EricN <eric@neilsonhart.com>]

On Jan 5, 4:28 pm, Alex Freed <alex_n...@mirrow.com> wrote:
> EricN wrote:
>
> > I also believe I have figured out the original logic used with the
> > 74LS00 which does the switching and debouncing using only three NAND
> > gates.  My hat is off to the Sr. Prom engineers for implementing such
> > an elegant minimalist logic solution. The schematic is here:
> >http://www.neilsonhart.com/seniorprom/SeniorPromSchem.bmp
>
> > Eric
>
> There is a little problem with this design - the NMI signal is supposed
> to be open collector. Only important if there is another board that can
> also assert the NMI signal. To be clean the LS00 should be replaced by a
> 74LS38 and a resistor (say 10k) added between pin 6 and +5V.
>
> BTW with a 74LS00 part R4 serves no purpose.
>
Thanks for that. Also, I discovered that my NMI is not debounced
properly after firing the NMI (the springback to normal position is
the error) so I'm going with Dutch's flip flop design with open
collector outputs.

Thanks,
Eric