In article <2C1375B7.29173@news.service.uci.edu> pho@vmsa.oac.uci.edu writes:
>* I'm posting this for my cousin Long *
>
>Sorry for the late reply. The 128k Zip GSX is technically a 64k/64k split
>cache. 64k is allocated for instruction cacheing and the other 64k is
>allocated for data cacheing. It is done by soldering four 32k x 8 static
>rams on top of another four, altering the cache logic with the addition
>of a 74F32 (OR gate), cutting two wire traces and a little bit of soldering.
>The Zip GSX can use two types of static ram, 8k x 8 and 32k x 8. It's
>possibly to use something like 128k x 8 if you can alter the cache logic.
Could you be more specific? Like wire what, where?
--
Glynne Tolar glynnet@zero.cypher.com
or GEnie: G.TOLAR