Re: 128k Zip GSX

[fmlin@netcom.com (Frank M. Lin)]

In article <2C1375B7.29173@news.service.uci.edu> pho@vmsa.oac.uci.edu writes:
>* I'm posting this for my cousin Long *
>
>In article <2C03EE31.26069@news.service.uci.edu> <C7ozF1.9xq@r-node.hub.org>
>fmlin@netcom.com (Frank M. Lin) writes...
>
>> How did you put 128k on the ZIP?  Higher density SRAMs?  I wonder if I
>> can do the same for TWGS ( if there are such SRAMs available )...
>
>Sorry for the late reply.  The 128k Zip GSX is technically a 64k/64k split
>cache.  64k is allocated for instruction cacheing and the other 64k is
>allocated for data cacheing.  It is done by soldering four 32k x 8 static
>rams on top of another four, altering the cache logic with the addition
>of a 74F32 (OR gate), cutting two wire traces and a little bit of soldering.
>The Zip GSX can use two types of static ram, 8k x 8 and 32k x 8.  It's
>possibly to use something like 128k x 8 if you can alter the cache logic.

If I'm reading you right, your Zip must look rather funky.   :>  With
doubled cache, was the improvment notcable?  128k looks like it took
a bit of work, and you're probably the only one with it.

-- 
frank m. lin
fmlin@netcom.com